关于晶振（晶体谐振器）在电路中的电磁兼容性（EMC）设计，总结如下：

For most digital applications, the crystal oscillator is a very critical frequency controlling component. It might control basic computing parameters such as accumulation interval, data updates, etc., but also the RTC. For some applications, the XOUT and XIN pins on the PCBA are connected to high-impedance circuitry which makes them potentially very sensitive to component selection and layout.

在大多数数字电路中，晶体振荡器是一个非常关键的频控元件。它可能控制最基本的计算参数，如累积间隔、数据更新等，另外还控制RTC（实时时钟）。对于一些应用方案，晶体谐振器的信号输出脚XOUT和信号输入脚XIN引脚会连接到高阻抗电路，这就意味着时钟信号对器件选择和布局非常敏感。

如某款芯片对两款晶振（晶体谐振器）的要求如下：

1、Both capacitors at the crystal should be ceramic capacitors with 27 pF capacitance.

与晶振匹配的两个电容器应该分别为27pF陶瓷电容器。

2、The crystal should be a 32.768kHz type with a load capacitance of 12.5 pF。

选择负载电容为12.5 pF的32.768 kHz晶体谐振器。

The crystal body (if a metal-can crystal is used) and the capacitors should have a separate ground, as shown in Figure below (blue lines). This ground should be connected to the board ground (GNDD) with a ferrite bead.

所选晶体谐振器（若为金属封装）和电容应该有一个单独的接地，如上图所示（蓝线）。这个地应该用磁珠连接地（GNDD）。

拓展阅读：Design for EMC电磁兼容性设计

Design for electromagnetic compatibility (EMC) must be a top priority from the very beginning of the design. 电磁兼容性（EMC）设计必须从产品设计一开始就成为重中之重。

EMC/EMI tests typically include常规EMC/EMI测试通常包括：

• Conducted and Radiated Emissions tests传导和辐射测试
• RF Immunity tests with and without load有无负载射频抗扰测试
• Electrostatic Discharge (ESD) tests静电放电（ESD）测试
• Electrical Fast transient (EFT) tests·脉冲（EFT）测试

Successfully passing these tests depends on many factors, including 成功通过这些测试取决于许多因素，包括：

• Schematic design and component selection最初原理图设计和器件选型
• Printed circuit board (PCB) topology, component placement, PCB design 电路板拓扑结构，元件布局，PCB布线设计
• Firmware code固件代码·